The present invention generally relates to a low cost, high volume processes for the assembly of ultra small die to three-dimensional (3D) or 2.5D semiconductor packages, and to structures, equipment, and apparatuses used in the processes.
There is a current need in the industry for both low cost and high volume ultra small die to package assembly manufacturing processes. These package assemblies can be used for applications where miniaturization of electronic devices is desired such as for mobile, IOT, wearable, smart phone, bio-compatible interface low power, light weight electronic systems, and the like.
In 3D chip stacks, chips or dice are layered on top of one another in a three-dimensional stack with electrical interconnects between layers. This configuration has many benefits, such as providing a designer with the ability to place an increased number of chips in a given two-dimensional area with an increased amount of electrical communications between them. In 2.5D packages, an interconnect substrate known as an interposer is used to provide high density interconnects. The interposer is placed between the substrate and the dice, where the interposer contains through silicon vias (TSVs) connecting the metallization layers on its upper and lower surfaces.